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never stop thinking. hyb18l256160bf-7.5 hye18l256160bf-7.5 hyb18l256160bc-7.5 hye18l256160bc-7.5 drams for mobile applications 256-mbit mobile-ram data sheet, v1.4, april 2004 memory products
edition 2004-04-30 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hyb18l256160bf-7.5 hye18l256160bf-7.5 hyb18l256160bc-7.5 hye18l256160bc-7.5 drams for mobile applications 256-mbit mobile-ram data sheet, v1.4, april 2004 memory products
template: mp_a4_v2.0_2003-06-06.fm hyb18l256160bf-7.5, hye18l256160bf-7.5, hyb18l256160bc-7.5, hye18l256160bc-7.5 revision history: v1.4 2004-04-30 45 table 20 : t t removed 47 table 23 : driver characteristics for half drive and full drive merged previous version: v1.3 (preliminary datasheet) 2003-03-19 12 power-up sequence: 2 instead of 8 arf commands required 47 table 22 : idd6 specification modified: typ. and max. values given previous version: v1.2 (preliminary datasheet) 2004-01-28 all package option with lead-containing (?black?) balls added previous version: v1.1 (preliminary datasheet) 2003-12-18 all -8 speed grade removed 39 deep power-down exit: clarification added 45 table 20 : t oh changed 46 table 21 : idd parameter values changed 48 package drawing updated previous version: v1.0 (preliminary datasheet) 2003-06-23 all converted to new datasheet template all sales code changed from ?af? to ?bf? 17 , 42 table 6 and table 16 : deep power down mode added 43 table 17 (absolute maximum ratings): max. v dd and v ddq values changed to 2.7v 46 table 21 : parameters i dd2ps , i dd2ns , i dd3ps and i dd3ns added previous version: v0.5 (target datasheet) 2003-02 all sales code changed from ?ac? to ?af? (green package) 7table2 (memory addressing scheme) added 19 figure 7 (mode register set command) corrected 35 description of concurrent auto precharge feature modified; figure 37 to figure 40 added 48 package height reduced to 1.0 mm previous version: v0.4 (target datasheet) 2002-11 47 table 23 : drive strength values changed previous version: v0.3 (target datasheet) 2002-11 15 tcsr: temperature sensor activated permanently, making tcsr bits ?don?t care? 46 table 21 : idd parameter test conditions clarified previous version: v0.2 (target datasheet) 2002-11 all complete new test layout, figures and tables 14 emrs: bits a5, a6 used for drive strength definition previous version: v0.1 (target datasheet, initial release) 2002-09-06 we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
data sheet 5 v1.4, 2004-04-30 hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 pin definition and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 power on and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1.1 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.1.2 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.1.3 read latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.1.4 write burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.1.5 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.1.6 partial array self refresh (pasr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.1.7 temperature compensated self refresh (tcsr) with on-chip temperature sensor . . . . . . . . 15 2.2.1.8 selectable drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.1 no operation (nop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4.2 deselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4.3 mode register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.4 active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4.5 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.5.1 read burst termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.5.2 clock suspend mode for read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.5.3 read - dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4.5.4 read to write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4.5.5 read to precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4.6 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.4.6.1 write burst termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4.6.2 clock suspend mode for write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4.6.3 write - dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.4.6.4 write to read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.4.6.5 write to precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4.7 burst terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4.8 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.8.1 auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.8.2 concurrent auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4.9 auto refresh and self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4.9.1 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4.9.2 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.4.10 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.4.10.1 deep power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.5 function truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3 operating currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.4 pullup and pulldown characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table of contents
data sheet 6 v1.4, 2004-04-30 hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram figure 1 standard ballout 256-mbit mobile-ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2 functional block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3 power-up sequence and mode register sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4 state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5 address / command inputs timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6 no operation command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7 mode register set command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8 mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9 active command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10 bank activate timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12 basic read timing parameters for dqs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 13 single read burst (cas latency = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14 single read burst (cas latency = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 15 consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 16 random read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 17 non-consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 18 terminating a read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 19 clock suspend mode for read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 20 read burst - dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 21 read to write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 22 read to precharge timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 23 write command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 24 basic write timing parameters for dqs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 25 write burst (cas latency = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 26 write burst (cas latency = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 27 consecutive write bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 28 random write bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 29 non-consecutive write bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 30 terminating a write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 31 clock suspend mode for write bursts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 32 write burst - dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 33 write to read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 34 write to precharge timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 35 burst terminate command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 36 precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 37 read with auto precharge interrupted by read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 38 read with auto precharge interrupted by write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 39 write with auto precharge interrupted by read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 40 write with auto precharge interrupted by write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 figure 41 auto refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 42 auto refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 43 self refresh entry command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 44 self refresh entry and exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 45 power down entry command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 46 power down entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 47 p-vfbga-54-2 (plastic very thin fine ball grid array package) . . . . . . . . . . . . . . . . . . . . . . . . . 48 list of figures
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram overview data sheet 7 v1.4, 2004-04-30 1 overview 1.1 features 4 banks 4 mbit 16 organization fully synchronous to positive clock edge four internal banks for concurrent operation programmable cas latency: 2, 3 programmable burst length: 1, 2, 4, 8 or full page programmable wrap sequence: sequential or interleaved programmable drive strength auto refresh and self refresh modes 8192 refresh cycles / 64 ms auto precharge commerical (0c to +70c) and extended (-25 o c to +85 o c) operating temperature range 54-ball p-vfbga package (12.0 8.0 1.0 mm) power saving features low supply voltages: v dd = 1.8 v 0.15 v, v ddq = 1.8 v 0.15 v optimized self refresh ( i dd6 ) and standby currents ( i dd2 / i dd3 ) programmable partial array self refresh (pasr) temperature compensated self-refresh (tcsr), controlled by on-chip temperature sensor power-down and deep power down modes table 1 performance part number speed code - 7.5 unit speed grade 133 mhz access time ( t acmax ) cl = 3 5.4 ns cl = 2 6.0 ns clock cycle time ( t ckmin ) cl = 3 7.5 ns cl = 2 9.5 ns table 2 memory addressing scheme item addresses banks ba0, ba1 rows a0 - a12 columns a0 - a8
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram overview data sheet 8 v1.4, 2004-04-30 1.2 pin configuration figure 1 standard ballout 256-mbit mobile-ram table 3 ordering information type 1) package description commercial temperature range hyb18l256160bc-7.5 p-vfbga-54-2 133 mhz 4 banks 4 mbit 16 lp-sdram hyb18l256160bf-7.5 p-vfbga-54-2 133 mhz 4 banks 4 mbit 16 lp-sdram extended temperature range hye18l256160bc-7.5 p-vfbga-54-2 133 mhz 4 banks 4 mbit 16 lp-sdram hye18l256160bf-7.5 p-vfbga-54-2 133 mhz 4 banks 4 mbit 16 lp-sdram 1) hyb / hye: designator for memory products (hyb: standard temp. range; hye: extended temp. range) 18l: 1.8v mobile-ram 256: 256 mbit density 160: 16 bit interface width b: die revision c / f: lead-containing product (c) / green product (f) -7.5: speed grade(s): min. clock cycle time v ssq udqm v ddq dq12 dq10 dq15 v ssq v ddq cke clk a9 a12 a8 a11 dq9 dq11 dq13 v ss 123 ba1 dq6 dq4 dq2 v dd 7 ldqm dq0 v ssq v ddq v ssq ba0 a1 a10/ap 8 v dd v ddq dq1 dq3 dq5 dq7 9 a b c d f g h j e cas ras we a0 a7 v ss a4 v dd a3 a2 a5 dq14 a6 v ss nc dq8 cs
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram overview data sheet 9 v1.4, 2004-04-30 1.3 description the hy[b/e]18l256160b[c/f] is a high-speed cmos, dynamic random-access memory containing 268,435,456 bits. it is internally configured as a quad-bank dram. the hy[b/e]18l256160b[c/f] achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to the system clock. read and write accesses are burst-oriented; accesses start at a selected location and continue for a programmed number of locations (1, 2, 4, 8 or full page) in a programmed sequence. the device operation is fully synchronous: all inputs are registered at the positive edge of clk. the hy[b/e]18l256160b[c/f] is especially designed for mobile applications. it operates from a 1.8v power supply. power consumption in self refresh mode is drastically reduced by an on-chip temperature sensor (octs); it can further be reduced by using the programmable partial array self refresh (pasr). a conventional data-retaining power-down (pd) mode is available as well as a non-data-retaining deep power- down (dpd) mode. the hy[b/e]18l256160b[c/f] is housed in a 54-ball p-vfbga package. it is available in commercial (0 c to 70 c) and extended (-25 c to +85 c) temperature range. figure 2 functional block diagram cke clk cs ras cas we address register row address mux 13 13 13 refresh counter command decode mode registers control logic bank 0 row address latch & decoder 13 bank column logic column address counter / latch 9 bank 0 memory array (8192 x 512 x 16) sense amplifier 8192 io gating dqm mask logic column decoder 9 15 a0-a12 ba0,ba1 16 dq0- dq15 data output reg. data input reg. 16 ldqm udqm bank 1 bank 2 bank 3 2 2 2 2
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram overview data sheet 10 v1.4, 2004-04-30 1.4 pin definition and description table 4 pin description ball type detailed function clk input clock: all inputs are sampled on the positive edge of clk. cke input clock enable: cke high activates and cke low deactivates internal clock signals, device input buffers and output drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), active power- down (row active in any bank) or suspend (access in progress). input buffers, excluding clk and cke are disabled during power-down. input buffers, excluding cke are disabled during self refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple memory banks. cs is considered part of the command code. ras , cas , we input command inputs: ras, cas and we (along with cs ) define the command being entered. dq0 - dq15 i/o data inputs/output: bi-directional data bus (16 bit) ldqm, udqm input input/output mask: input mask signal for write cycles and output enable for read cycles. for writes, dqm acts as a data mask when high. for reads, dqm acts as an output enable and places the output buffers in high-z state when high (two clocks latency). ldqm corresponds to the data on dq0 - dq7; udqm to the data on dq8 - dq15. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an activate, read, write or precharge command is being applied. ba0, ba1 also determine which mode register is to be loaded during a mode register set command (mrs or emrs). a0 - a12 input address inputs: a0 - a12 define the row address during an active command cycle. a0 - a8 define the column address during a read or write command cycle. in addition, a10 (= ap) controls auto precharge operation at the end of the burst read or write cycle. during a precharge command, a10 (= ap) in conjunction with ba0, ba1 controls which bank(s) are to be precharged: if a10 is high, all four banks will be precharged regardless of the state of ba0 and ba1; if a10 is low, ba0, ba1 define the bank to be precharged. during mode register set commands, the address inputs hold the op- code to be loaded. v ddq supply i/o power supply: isolated power for dq output buffers for improved noise immunity: v ddq = 1.8 v 0.15 v v ssq supply i/o ground v dd supply power supply: power for the core logic and input buffers, v dd = 1.8 v 0.15 v v ss supply ground n.c. ? no connect
data sheet 11 v1.4, 2004-04-30 hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description 2 functional description the 256-mbit mobile-ram is a high-speed cmos, dynamic random-access memory containing 268,435,456 bits. it is internally configured as a quad-bank dram. read and write accesses to the mobile-ram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the banks, a0 - a12 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the mobile-ram must be initialized. the following sections provide detailed information covering device initialization, register definition, command description and device operation. 2.1 power on and initialization the mobile-ram must be powered up and initialized in a predefined manner (see figure 3 ). operational procedures other than those specified may result in undefined operation. figure 3 power-up sequence and mode register sets power-up: vdd and ck stable load mode register load ext. mode register = don't care ba0=l ba1=h t rfc t rfc t mrd t mrd t rp 200s t ck all banks dq (high-z) dqm ba0,ba1 nop ba a10 code nop ra code address code nop ra code command pre arf arf mrs nop nop act mrs clk ba0=l ba1=l (h level) vdd vddq cke
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description data sheet 12 v1.4, 2004-04-30 1. at first, device core power ( v dd ) and device io power ( v ddq ) must be brought up simultaneously. typically v dd and v ddq are driven from a single power converter output. assert and hold cke and dqm to a high level. 2. after v dd and v ddq are stable and cke is high, apply stable clocks. 3. wait for 200s while issuing nop or deselect commands. 4. issue a precharge all command, followed by nop or deselect commands for at least t rp period. 5. issue two auto refresh commands, each followed by nop or deselect commands for at least t rfc period. 6. issue two mode register set commands for programming the mode register and extended mode register, each followed by nop or deselect commands for at least t mrd period; the order in which both registers are programmed is not important. following these steps, the mobile-ram is ready for normal operation. 2.2 register definition 2.2.1 mode register the mode register is used to define the specific mode of operation of the mobile-ram. this definition includes the selection of a burst length (bits a0-a2), a burst type (bit a3), a cas latency (bits a4-a6), and a write burst mode (bit a9). the mode register is programmed via the mode register set command (with ba0 = 0 and ba1 = 0) and will retain the stored information until it is programmed again or the device loses power. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. violating either of these requirements results in unspecified operation. reserved states should not be used, as unknown operation or incompatibility with future versions may result. mr mode register definition (ba[1:0] = 00 b ) ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 00000wb00 cl bt bl field bits type description wb 9w write burst mode 0burst write 1 single write cl [6:4] w cas latency 010 2 011 3 note: all other bit combinations are reserved. bt 3w burst type 0 sequential 1 interleaved bl [2:0] w burst length 000 1 001 2 010 4 011 8 111 full page (sequential burst type only) note: all other bit combinations are reserved.
data sheet 13 v1.4, 2004-04-30 hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description 2.2.1.1 burst length read and write accesses to the mobile-ram are burst oriented, with the burst length being programmable. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4, 8 locations are available for both the sequential and interleaved burst types, and a full-page burst mode is available for the sequential burst type. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. the block is uniquely selected by a1-a8 when the burst length is set to two, by a2-a8 when the burst length is set to four and by a3-a8 when the burst length is set to eight. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full page bursts wrap within the page if the boundary is reached. please note that full page bursts do not self- terminate; this implies that full-page read or write bursts with auto precharge are not legal commands. notes 1. for a burst length of 2, a1-ai select the two-data-element block; a0 selects the first access within the block. 2. for a burst length of 4, a2-ai select the four-data-element block; a0-a1 select the first access within the block. 3. for a burst length of 8, a3-ai select the eight-data-element block; a0-a2 select the first access within the block. 4. for a full page burst, a0-ai select the starting data element. 5. whenever a boundary of the block is reached within a given sequence, the following access wraps within the block. 2.2.1.2 burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 5 . table 5 burst definition burst length starting column address order of accesses within a burst a2 a1 a0 sequential interleaved 200 - 10 - 1 11 - 0 1 - 0 4 0 0 0 - 1 - 2 - 3 0 - 1 - 2 - 3 0 1 1 - 2 - 3 - 0 1 - 0 - 3 - 2 1 0 2 - 3 - 0 - 1 2 - 3 - 0 - 1 1 1 3 - 0 - 1 - 2 3 - 2 - 1 - 0 8 0 0 0 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0 0 1 1 - 2 - 3 - 4 - 5 - 6 - 7 - 0 1 - 0 - 3 - 2 - 5 - 4 - 7 - 6 0 1 0 2 - 3 - 4 - 5 - 6 - 7 - 0 - 1 2 - 3 - 0 - 1 - 6 - 7 - 4 - 5 0 1 1 3 - 4 - 5 - 6 - 7 - 0 - 1 - 2 3 - 2 - 1 - 0 - 7 - 6 - 5 - 4 1 0 0 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 1 0 1 5 - 6 - 7 - 0 - 1 - 2 - 3 - 4 5 - 4 - 7 - 6 - 1 - 0 - 3 - 2 1 1 0 6 - 7 - 0 - 1 - 2 - 3 - 4 - 5 6 - 7 - 4 - 5 - 2 - 3 - 0 - 1 1 1 1 7 - 0 - 1 - 2 - 3 - 4 - 5 - 6 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 full page n n n cn, cn+1, cn+2, ? not supported
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description data sheet 14 v1.4, 2004-04-30 2.2.1.3 read latency the read latency, or cas latency, is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the latency can be programmed to 2 or 3 clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available with clock edge n + m (for details please refer to the read command description). 2.2.1.4 write burst mode when a9 = 0, the burst length programmed via a0-a2 applies to both read and write bursts; when a9 = 1, write accesses consist of single data elements only. 2.2.1.5 extended mode register the extended mode register controls additional low power features of the device. these include the partial array self refresh (pasr, bits a0-a2)), the temperature compensated self refresh (tcsr, bits a3-a4)) and the drive strength selection for the dqs (bits a5-a6). the extended mode register is programmed via the mode register set command (with ba0 = 0 and ba1 = 1) and will retain the stored information until it is programmed again or the device loses power. the extended mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. violating either of these requirements result in unspecified operation. reserved states should not be used, as unknown operation or incompatibility with future versions may result. 2.2.1.6 partial array self refresh (pasr) partial array self refresh is a power-saving feature specific to mobile rams. with pasr, self refresh may be restricted to variable portions of the total array. the selection comprises all four banks (default), two banks, one bank, half of one bank, and a quarter of one bank. data written to the non activated memory sections will get lost after a period defined by t ref (cf. table 13 ). emr extended mode register (ba[1:0] = 10 b ) ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 10000000 ds (tcsr) pasr field bits type description ds [6:5] w selectable drive strength 00 full drive strength 01 half drive strength note: all other bit combinations are reserved. tcsr [4:3] w temperature compensated self refresh xx superseded by on-chip temperature sensor (see text) pasr [2:0] w partial array self refresh 000 all banks 001 1/2 array (ba1 = 0) 010 1/4 array (ba1 = ba0 = 0) 101 1/8 array (ba1 = ba0 = ra12 = 0) 110 1/16 array (ba1 = ba0 = ra12 = ra11 = 0) note: all other bit combinations are reserved.
data sheet 15 v1.4, 2004-04-30 hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description 2.2.1.7 temperature compensated self re fresh (tcsr) with on-chip temperature sensor dram devices store data as electrical charge in tiny capacitors that require a periodic refresh in order to retain the stored information. this refresh requirement heavily depends on the die temperature: high temperatures correspond to short refresh periods, and low temperatures correspond to long refresh periods. the mobile-ram is equipped with an on-chip temperature sensor which continuously senses the actual die temperature and adjusts the refresh period in self refresh mode accordingly. this makes any programming of the tcsr bits in the extended mode register obsolete. it also is the superior solution in terms of compatibility and power-saving, because it is fully compatible to all processors that do not support the extended mode register it is fully compatible to all applications that only write a default (worst case) tcsr value, e.g. because of the lack of an external temperature sensor it does not require any processor interaction for regular tcsr updates 2.2.1.8 selectable drive strength the drive strength of the dq output buffers is selectable via bits a5 and a6. the default value (?half drive strength?) is suitable for typical applications of a mobile-ram. for heavier loaded systems, a stronger output buffer (?full drive strength?) is available. i - v curves for the full drive strength and half drive strength are included in this document.
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description data sheet 16 v1.4, 2004-04-30 2.3 state diagram figure 4 state diagram power on mode register set power applied deep power down dpdsx mrs act self refresh refs refsx idle dpds auto refresh refa active power down ckeh ckel row active w r i t e read write a read a precharge read reada writea reada writea pre read a pre automatic sequence command sequence clock suspend read clock suspend reada clock suspend write clock suspend writea r e a d b s t b s t ckel ckel ckel ckel ckeh ckeh ckeh ckeh preall = precharge all banks refs = enter self refresh refsx = exit self refresh refa = auto refresh dpds = enter deep power down dpdsx = exit deep power down ckel = enter power down ckeh = exit power down read = read w/o auto precharge reada = read with auto precharge write = write w/o auto precharge writea = write with auto precharge precharge all preall ckel ckeh precharge power down write writea write pre pre act = active pre = precharge bst = burst terminate mrs = mode register set
data sheet 17 v1.4, 2004-04-30 hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description 2.4 commands address (a0 - a12, ba0, ba1), write data (dq0 - dq15) and command inputs (cke, cs , ras , cas , we , dqm) are all registered on the positive edge of clk. figure 5 shows the basic timing parameters, which apply to all commands and operations. figure 5 address / command inputs timing parameters table 6 command overview command cs ras cas we dqm address notes nop deselect h x x x x x 1) 1) deselect and nop are functionally interchangeable. no operation l h h h x x 1) act active (select bank and row) l l h h x bank / row 2) 2) ba0, ba1 provide bank address, and a0 - a12 provide row address. rd read (select bank and column and start read burst) l h l h l/h bank / col 3) 3) ba0, ba1 provide bank address, a0 - a8 provide column address; a10 high enables the auto precharge feature (nonpersistent), a10 low disables the auto precharge feature. wr write (select bank and column and start write burst) l h l l l/h bank / col 3) bst burst terminate or deep power down lh h l x x 4) 4) this command is burst terminate if cke is high, deep power down if cke is low. the burst terminate command is defined for read or write bursts with auto precharge disabled only. pre precharge (deactivate row in bank or banks) l l h l x code 5) 5) a10 low: ba0, ba1 determine which bank is precharged. a10 high: all banks are precharged and ba0, ba1 are ?don?t care?. arf auto refresh or self refresh (enter self refresh mode) ll lh x x 6)7) 6) this command is auto refresh if c ke is high, self refresh if cke is low. 7) internal refresh counter controls row and bank addressing; all inputs and i/os are ?don?t care? except for cke. mrs mode register set l l l l x op-code 8) 8) ba0, ba1 select either the mode register (ba0 = 0, ba1 = 0) or the extended mode register (ba0 = 0, ba1 = 1); other combinations of ba0, ba1 are reserved; a0 - a12 provide the op-code to be written to the selected mode register. ? data write / output enable ? ? ? ? l ? 9) 9) dqm low: data present on dqs is written to memory during write cycles; dq output buffers are enabled during read cycles; dqm high: data present on dqs are masked and thus not written to memory during write cycles; dq output buffers are placed in high-z state (two clocks latency) during read cycles. ? write mask / output disable (high-z) ? ? ? ? h ? 9) = don't care t cl t ch t is t ih t ck clk input *) valid valid valid *) = a0 - a12, ba0, ba1, cs, cke, ras, cas, we
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description data sheet 18 v1.4, 2004-04-30 2.4.1 no operation (nop) figure 6 no operation command the no operation (nop) command is used to perform a nop to a mobile-ram which is selected (cs = low). this prevents unwanted commands from being registered during idle states. operations already in progress are not affected. 2.4.2 deselect the deselect function (cs = high) prevents new commands from being executed by the mobile-ram . the mobile-ram is effectively deselected. operations already in progress are not affected. table 7 inputs timing parameters parameter symbol - 7.5 unit notes min. max. clock cycle time cl = 3 t ck 7.5 ? ns ? cl = 2 9.5 ? ns clock frequency cl = 3 f ck ? 133 mhz ? cl = 2 ? 105 mhz clock high-level width t ch 2.5 ? ns ? clock low-level width t cl 2.5 ? ns ? address and command input setup time t is 1.5 ? ns ? address and command input hold time t ih 0.8 ? ns ? = don't care we cas cs cke (high) clk a0-a12 ba0,ba1 ras
data sheet 19 v1.4, 2004-04-30 hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description 2.4.3 mode register set figure 7 mode register set command the mode register and extended mode register are loaded via inputs a0 - a12 (see mode register descriptions in chapter 2.2 ). the mode register set command can only be issued when all banks are idle and no bursts are in progress. a subsequent executable command cannot be issued until t mrd is met. figure 8 mode register definition = don't care cs cke (high) clk a0-a12 code ba0,ba1 code we cas ras table 8 timing parameters for mode register set command parameter symbol - 7.5 units notes min. max. mode register set command period t mrd 2? t ck ? code = mode register / extended mode register selection (ba0, ba1) and op-code (a0 - a12) t mrd = don't care clk command mrs nop valid address code valid
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description data sheet 20 v1.4, 2004-04-30 2.4.4 active figure 9 active command before any read or write commands can be issued to a bank within the mobile-ram , a row in that bank must be ?opened? (activated). this is accomplished via the active command and addresses a0 - a12, ba0 and ba1 (see figure 9 ), which decode and select both the bank and the row to be activated. after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the t rcd specification. a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the minimum time interval between successive active commands to the same bank is defined by t rc . a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active commands to different banks is defined by t rrd . figure 10 bank activate timings = don't care ba = bank address ra = row address ba0,ba1 ba a0-a12 ra we cas ras cs cke (high) clk table 9 timing parameters for active command parameter symbol - 7.5 units notes min. max. active to active command period t rc 67 ? ns 1) 1) these parameters account for the number of clock cycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period; round up to next integer. active to read or write delay t rcd 19 ? ns 1) active bank a to active bank b delay t rrd 15 ? ns 1) t rrd t rcd = don't care clk rd/wr nop nop nop act nop act command row row col a0-a12 ba x ba y ba y ba0, ba1
data sheet 21 v1.4, 2004-04-30 hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description 2.4.5 read figure 11 read command subsequent to programming the mode register with cas latency and burst length, read bursts are initiated with a read command, as shown in figure 11 . basic timings for the dqs are shown in figure 12 ; they apply to all read operations and therefore are omitted from all subsequent timing diagrams. the starting column and bank addresses are provided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed starts precharge at the completion of the burst, provided t ras has been satisfied. for the generic read commands used in the following illustrations, auto precharge is disabled. figure 12 basic read timing parameters for dqs ba0,ba1 ba we cke (high) clk ras cas a0-a8 ca = don't care ba = bank address ca = column address ap = auto precharge a10 ap disable ap enable ap cs t lz t ac t ac t hz clk = don't care t dqz t oh t oh dqm dq do n+1 do n
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description data sheet 22 v1.4, 2004-04-30 during read bursts, the valid data-out element from the starting column address is available following the cas latency after the read command. each subsequent data-out element is valid nominally at the next positive clock edge. upon completion of a read burst, assuming no other read command has been initiated, the dqs go to high-z state. figure 13 and figure 14 show single read bursts for each supported cas latency setting. figure 13 single read burst (cas latency = 2) table 10 timing parameters for read parameter symbol - 7.5 units notes min. max. access time from clk cl = 3 t ac ?5.4ns? cl = 2 t ac ?6.0ns dq low-impedance time from clk t lz 1.0 ? ns ? dq high-impedance time from clk t hz 3.0 7.0 ns data out hold time t oh 2.5 ? ns ? dqm to dq high-z delay (read commands) t dqz ?2 t ck ? active to active command period t rc 67 ? ns 1) active to read or write delay t rcd 19 ? ns 1) active to precharge command period t ras 45 100k ns 1) precharge command period t rp 19 ? ns 1) 1) these parameters account for the number of clock cycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period; round up to next integer. ba a, col n = bank a, column n do n = data out from column n burst length = 4 in the case shown. 3 subsequent elements of data out are provided in the programmed order following do n. = don't care cl=2 t rcd t ras t rc t rp clk command nop read nop nop nop pre nop act act address ba a, row b ba a, col n ba a, row x a10 (ap) pre bank a pre all dis ap row x row b ap do n+1 do n do n+2 do n+3 dq ap = auto precharge dis ap = disable auto precharge
data sheet 23 v1.4, 2004-04-30 hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description figure 14 single read burst (cas latency = 3) data from any read burst may be concatenated with data from a subsequent read command. in either case, a continuous flow of data can be maintained. a read command can be initiated on any clock cycle following a previous read command, and may be performed to the same or a different (active) bank. the first data element from the new burst follows either the last element of a completed burst ( figure 15 ) or the last desired data element of a longer burst which is being truncated ( figure 16 ). the new read command should be issued x cycles after the first read command, where x equals the number of desired data elements. figure 15 consecutive read bursts ba a, col n = bank a, column n do n = data out from column n burst length = 4 in the case shown. 3 subsequent elements of data out are provided in the programmed order following do n. = don't care cl=3 t rcd t rp t ras t rc command nop read nop nop nop pre nop act act nop nop clk ap = auto precharge dis ap = disable auto precharge address a10 (ap) pre bank a pre all dis ap dq do n+1 do n do n+2 do n+3 ba a, row b row b ba a, row x row x ba a, col n ap ba a, col n (b) = bank a, column n (b) do n (b) = data out from column n (b) burst length = 4 in the case shown. 3 subsequent elements of data out are provided in the programmed order following do n (b). = don't care clk cl=2 cl=3 command nop read nop nop nop nop nop read nop address ba a, col b ba a, col n dq do n+1 do n do n+2 do n+3 do b+2 do b do b+1 dq do n+1 do n do n+2 do n+3 do b+1 do b
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description data sheet 24 v1.4, 2004-04-30 figure 16 random read bursts non-consecutive read bursts are shown in figure 17 . figure 17 non-consecutive read bursts ba a, col n etc. = bank a, column n etc. do n etc. = data out from column n etc. burst length = 4 in the case shown; bursts are terminated by consecutive read commands 3 subsequent elements of data out are provided in the programmed order following do m. = don't care clk cl=2 cl=3 command read nop nop nop nop read read read nop ba a, col n ba a, col a ba a, col x ba a, col m address dq do m+2 do m+3 do a do n do x do m+1 do m dq do m+2 do a do n do x do m+1 do m ba a, col n (b) = bank a, column n (b) do n (b) = data out from column n (b) burst length = 4 in the case shown. 3 subsequent elements of data out are provided in the programmed order following do n (b). cl=2 cl=3 = don't care clk command nop read nop nop nop nop nop read nop ba a, col n address ba a, col b dq do n+1 do n do n+2 do n+3 do b+1 do b dq do n+1 do n do n+2 do n+3 do b
data sheet 25 v1.4, 2004-04-30 hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description 2.4.5.1 read burst termination data from any read burst may be truncated using the burst terminate command (see page 33 ), provided that auto precharge was not activated. the burst terminate latency is equal to the cas latency, i.e. the burst terminate command must be issued x clock cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency for read bursts minus 1. this is shown in figure 18 . the burst terminate command may be used to terminate a full-page read which does not self-terminate. figure 18 terminating a read burst 2.4.5.2 clock suspend mode for read cycles clock suspend mode allows to extend any read burst in progress by a variable number of clock cycles. as long as cke is registered low, the following internal clock pulse(s) will be ignored and data on dq will remain driven, as shown in figure 19 . figure 19 clock suspend mode for read bursts ba a, col n = bank a, column n do n = data out from column n burst length = 4 in the case shown. 2 subsequent elements of data out are provided in the programmed order following do n. the burst is terminated after the 3rd data element. = don't care clk cl=2 cl=3 command nop read nop nop nop nop nop bst nop address ba a, col n dq do n+1 do n do n+2 dq do n+1 do n do n+2 ba a, col n etc. = bank a, column n etc. do n etc. = data out from column n etc. cl = 2 in the case shown clock suspend latency t csl is 1 clock cycle = don't care clk t csl t csl t csl cke internal clock command read nop nop nop nop nop ba a, col n address dq do n+2 do n do n+1 do n+1
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description data sheet 26 v1.4, 2004-04-30 2.4.5.3 read - dqm operation dqm may be used to suppress read data and place the output buffers into high-z state. the generic timing parameters as listed in table 10 also apply to this dqm operation. the read burst in progress is not affected and will continue as programmed. figure 20 read burst - dqm operation 2.4.5.4 read to write a read burst may be followed by or truncated with a write command. the write command can be performed to the same or a different (active) bank. care must be taken to avoid bus contention on the dqs; therefore it is recommended that the dqs are held in high-z state for a minimum of 1 clock cycle. this can be achieved by either delaying the write command, or suppressing the data-out from the read by pulling dqm high two clock cycles prior to the write command, as shown in figure 21 . with the registration of the write command, dqm acts as a write mask: when asserted high, input data will be masked and no write will be performed. figure 21 read to write timing ba a, col n = bank a, column n do n = data out from column n cl = 2 in the case shown. dqm read latency t dqz is 2 clock cycles = don't care clk command nop read nop nop nop nop nop nop dqm t dqz address ba a, col n dq do n+2 do n do n+3 ba a, col n (b) = bank a, column n (b) do n = data out from column n; di b = data in to column b; dqm is asserted high to set dqs to high-z state for 1 clock cycle prior to the write command. = don't care clk cl=2 cl=3 command nop read nop nop nop nop nop write address ba a, col b ba a, col n dqm dq do n di b di b+1 do n+1 high-z di b+2 dq di b di b+1 do n high-z di b+2
data sheet 27 v1.4, 2004-04-30 hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description 2.4.5.5 read to precharge a read burst may be followed by, or truncated with a precharge command to the same bank, provided that auto precharge was not activated. this is shown in figure 22 . the precharge command should be issued x clock cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency for read bursts minus 1. following the precharge command, a subsequent active command to the same bank cannot be issued until t rp is met. please note that part of the row precharge time is hidden during the access of the last data elements. in the case of a read being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same read burst with auto precharge enabled. the disadvantage of the precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts. figure 22 read to precharge timing ba a, col n = bank a, column n; ba am row = bank a, row x do n = data out from column n burst length = 4 in the case shown. cas latency = 3 in the case shown 3 subsequent elements of data out are provided in the programmed order following do n. = don't care cl=3 clk t rp command nop read nop nop nop nop act pre ba a, row a address ba a ba a, col n dis ap pre bank a pre all a10 (ap) ap dq do n+1 do n do n+2 do n+3
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description data sheet 28 v1.4, 2004-04-30 2.4.6 write figure 23 write command write bursts are initiated with a write command, as shown in figure 23 . basic timings for the dqs are shown in figure 24 ; they apply to all write operations. the starting column and bank addresses are provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the write burst. for the generic write commands used in the following illustrations, auto precharge is disabled. figure 24 basic write timing parameters for dqs during write bursts, the first valid data-in element is registered coincident with the write command, and subsequent data elements are registered on each successive positive edge of clk. upon completion of a burst, assuming no other commands have been initiated, the dqs remain in high-z state, and any additional input data is ignored. figure 25 and figure 26 show a single write burst for each supported cas latency setting. ba0,ba1 ba cs cke (high) clk ras cas a0-a8 ca = don't care ba = bank address ca = column address ap = auto precharge a10 ap disable ap enable ap we clk = don't care t is t ih t is t ih dqm dq di n di n+2
data sheet 29 v1.4, 2004-04-30 hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description figure 25 write burst (cas latency = 2) figure 26 write burst (cas latency = 3) table 11 timing parameters for write parameter symbol - 7.5 units notes min. max. dq and dqm input setup time t is 1.5 ? ns ? dq and dqm input hold time t ih 0.8 ? ns ? dqm write mask latency t dqw 0? t ck ? active to active command period t rc 67 ? ns 1) active to read or write delay t rcd 19 ? ns 1) active to precharge command period t ras 45 100k ns 1) write recovery time t wr 14 ? ns 1) precharge command period t rp 19 ? ns 1) 1) these parameters account for the number of clock cycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period; round up to next integer. ba a, col n = bank a, column n di n = data in to column n burst length = 4 in the case shown. 3 subsequent elements of data in are provi ded in the programmed order following di n. = don't care clk t rcd t ras t rc t rp t wr command nop write nop nop nop pre nop act act nop address ba a, row x ba a, col n ba a, row b row x row b dis ap ap pre bank a pre all a10 (ap) dq di n di n+2 di n+3 di n+1 ba a, col n = bank a, column n di n = data in to column n burst length = 4 in the case shown. 3 subsequent elements of data in are provi ded in the programmed order following di n. = don't care t rcd t ras t rc t rp t wr clk command nop write nop nop nop pre nop act act nop nop nop address ba a, row n ba a, col n ba a, row b pre bank a pre all row x dis ap ap row b a10 (ap) dq di n di n+2 di n+3 di n+1
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description data sheet 30 v1.4, 2004-04-30 data for any write burst may be concatenated with or truncated with a subsequent write command. in either case, a continuous flow of input data can be maintained. a write command can be issued on any positive edge of clock following the previous write command. the first data element from the new burst is applied after either the last element of a completed burst ( figure 27 ) or the last desired data element of a longer burst which is being truncated ( figure 28 ). the new write command should be issued x cycles after the first write command, where x equals the number of desired data elements. figure 27 consecutive write bursts figure 28 random write bursts non-consecutive write bursts are shown in figure 29 . figure 29 non-consecutive write bursts ba a, col n (b) = bank a, column n (b) di n (b) = data in to column n (b) burst length = 4 in the case shown. 3 subsequent elements of data in are provided in the programmed order following di n (b). command nop nop nop nop nop nop nop write write clk address ba a, col b ba a, col n dq di n di n+1 di n+2 di n+3 di b di b+1 di b+2 di b+3 = don't care ba a, col n etc. = bank a, column n etc. di n etc. = data in to column n etc. burst length = 4 in the case shown; bursts are terminated by consecutive write commands. 3 subsequent elements of data in are provided in the programmed order following di m . = don't care clk command nop nop nop nop nop write write write write address ba a, col m ba a, col x ba a, col a ba a, col n dq di n di a di x di m di m+1 di m+2 di m+3 ba a, col n (b) = bank a, column n (b) di n (b) = data in to column n (b) burst length = 4 in the case shown. 3 subsequent elements of data in are provided in the programmed order following di n (b). = don't care clk write command nop nop nop nop nop nop nop write ba a, col n address ba a, col b di b dq di n di n+1 di n+2 di n+3 di b+1 di b+2
data sheet 31 v1.4, 2004-04-30 hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description 2.4.6.1 write burst termination data from any write burst may be truncated using the burst terminate command (see page 33 ), provided that auto precharge was not activated. the input data provided coincident with the burst terminate command will be ignored. this is shown in figure 30 . the burst terminate command may be used to terminate a full-page write which does not self-terminate. figure 30 terminating a write burst 2.4.6.2 clock suspend mode for write cycles clock suspend mode allows to extend any write burst in progress by a variable number of clock cycles. as long as cke is registered low, the following internal clock pulse(s) will be ignored and no data will be captured, as shown in figure 31 . figure 31 clock suspend mode for write bursts ba a, col n = bank a, column n di n = data in to column n burst length = 4 in the case shown. 2 subsequent elements of data in are written in the programmed order following di n. the burst is terminated after the 3rd data element. = don't care clk command nop nop bst nop nop write nop address ba a, col n dq di n di n+1 di n+2 ba a, col n etc. = bank a, column n etc. do n etc. = data out from column n etc. cl = 2 in the case shown clock suspend latency t csl is 1 clock cycle clk cke internal clock command nop nop nop write nop ba a, col n address dq di n+2 di n di n+1 = don't care t csl t csl t csl
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description data sheet 32 v1.4, 2004-04-30 2.4.6.3 write - dqm operation dqm may be used to mask write data: when asserted high, input data will be masked and no write will be performed. the generic timing parameters as listed in table 11 also apply to this dqm operation. the write burst in progress is not affected and will continue as programmed. figure 32 write burst - dqm operation 2.4.6.4 write to read a write burst may be followed by, or truncated with a read command. the read command can be performed to the same or a different (active) bank. with the registration of the read command, data inputs will be ignored and no write will be performed, as shown in figure 33 . figure 33 write to read timing ba a, col n = bank a, column n di n = data in to column n burst length = 4 in the case shown. 3 subsequent elements of data in are provided in the programmed order following di n, with the first element (di n+1) being masked. dqm write latency is 0 clock cycles. = don't care clk command nop nop nop nop nop write address ba a, col n dqm dq di n di n+2 di n+3 ba a, col n (b) = bank a, column n (b) di n = data in to column n; do b = data out from column b; burst length = 4 in the case shown. 3 subsequent elements of data in (out) are provided in the programmed order following di n (do b). di n+3 is ignored due to read command. no dqm masking required at this point. = don't care clk write data are ignored cl=2 cl=3 command nop read nop nop nop nop nop write address ba a, col b ba a, col n dq do b do b+1 do b+2 di n di n+1 di n+2 high-z dq do b di b+1 di n di n+1 di n+2 high-z
data sheet 33 v1.4, 2004-04-30 hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description 2.4.6.5 write to precharge a write burst may be followed by, or truncated with a precharge command to the same bank, provided that auto precharge was not activated. this is shown in figure 34 . the precharge command should be issued t wr after the clock edge at which the last desired data element of the write burst was registered. additionally, when truncating a write burst, dqm must be pulled to mask input data presented during t wr prior to the precharge command. following the pre-charge command, a subsequent active command to the same bank cannot be issued until t rp is met. in the case of a write being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same write burst with auto precharge enabled. the disadvantage of the precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts. figure 34 write to precharge timing 2.4.7 burst terminate figure 35 burst terminate command the burst terminate command is used to truncate read or write bursts (with auto precharge disabled). the most recently registered read or write command prior to the burst terminate command will be truncated, as shown in figure 18 and figure 30 , respectively. the burst terminate command is not allowed for truncation of read or write bursts with auto precharge enabled. ba a, col n = bank a, column n di n = data in to column n burst length = 4 in the case shown. 3 subsequent elements of data in are provided in the programmed order following di n. di n+3 is masked due to dqm pulled high during t wr period prior to precharge command. = don't care dq di n di n+1 di n+2 t rp t wr clk dqm command nop nop nop nop nop act pre write address ba a, col n ba a, row a ba a dis ap pre bank a pre all a10 (ap) ap ap = auto precharge dis ap = disable auto precharge = don't care cas cs cke (high) clk a0-a12 ba0,ba1 we ras
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description data sheet 34 v1.4, 2004-04-30 2.4.8 precharge figure 36 precharge command the precharge command is used to deactivate (close) the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care?. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command will be treated as a nop if there is no open row in that bank, or if the previously open row is already in the process of precharging. 2.4.8.1 auto precharge auto precharge is a feature which performs the same individual-bank precharge functions described above, but without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge ( t rp ) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as described for each burst type. ba0,ba1 ba cs cke (high) clk = don't care ba = bank address (if a10 = l, otherwise don't care) ras cas we a10 one bank all banks a0-a9 a11,a12 table 12 timing parameters for precharge parameter symbol - 7.5 units notes min. max. active to precharge command period t ras 45 100k ns 1) 1) these parameters account for the number of clock cycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period; round up to next integer. write recovery time t wr 14 ? ns 1) precharge command period t rp 19 ? ns 1)
data sheet 35 v1.4, 2004-04-30 hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description 2.4.8.2 concurrent auto precharge a read or write burst with auto precharge enabled can be interrupted by a subsequent read or write command issued to a different bank. figure 37 shows a read with auto precharge to bank n, interrupted by a read (with or without auto precharge) to bank m. the read to bank m will interrupt the read to bank n, cas latency later. the precharge to bank n will begin when the read to bank m is registered. figure 38 shows a read with auto precharge to bank n, interrupted by a write (with or without auto precharge) to bank m. the precharge to bank n will begin when the write to bank m is registered. dqm should be pulled high two clock cycles prior to the write to prevent bus contention. figure 39 shows a write with auto precharge to bank n, interrupted by a read (with or without auto precharge) to bank m. the precharge to bank n will begin t wr after the new command to bank m is registered. the last valid data-in to bank n is one clock cycle prior to the read to bank m. figure 40 shows a write with auto precharge to bank n, interrupted by a write (with or without auto precharge) to bank m. the precharge to bank n will begin t wr after the write to bank m is registered. the last valid data-in to bank n is one clock cycle prior to the write to bank m. figure 37 read with auto precharge interrupted by read figure 38 read with auto precharge interrupted by write rd-ap = read with auto precharge; read = read with or without auto precharge cl = 2 and burst length = 4 in the case shown read with auto precharge to bank n is interrupted by subsequent read to bank m = don't care cl=2 clk command rd-ap nop nop nop read nop nop nop address bank n col b bank m col x dq do b+1 do b do x do x+1 do x+2 t rp (bank n) rd-ap = read with auto precharge; write = write with or without auto precharge cl = 2 and burst length = 4 in the case shown read with auto precharge to bank n is interrupted by subsequent write to bank m = don't care cl=2 dqm clk command nop rd-ap nop nop nop nop write nop address bank m col x bank n col b dq do b di x+1 di x+2 di x+3 di x t rp (bank n)
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description data sheet 36 v1.4, 2004-04-30 figure 39 write with auto precharge interrupted by read figure 40 write with auto precharge interrupted by write wr-ap = write with auto precharge; read = read with or without auto precharge cl = 2 and burst length = 4 in the case shown write with auto precharge to bank n is interrupted by subsequent read to bank m = don't care clk command nop nop nop read nop address bank n col b bank m col x nop nop wr-ap t wr (bank n) t rp (bank n) dq do x do x+1 do x+3 do b+1 do b do x+2 cl=2 wr-ap = write with auto precharge; write = write with or without auto precharge burst length = 4 in the case shown write with auto precharge to bank n is interrupted by subsequent write to bank m = don't care clk t rp (bank n) t wr (bank n) command nop nop nop write nop wr-ap nop nop address bank n col b bank m col x dq di b+1 di b di x di x+1 di x+1 di x+1
data sheet 37 v1.4, 2004-04-30 hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description 2.4.9 auto refresh and self refresh the mobile-ram requires a refresh of all rows in a rolling interval. each refresh is generated in one of two ways: by an explicit auto refresh command, or by an internally timed event in self refresh mode. 2.4.9.1 auto refresh figure 41 auto refresh command auto refresh is used during normal operation of the mobile-ram . the command is nonpersistent, so it must be issued each time a refresh is required. a minimum row cycle time ( t rc ) is required between two auto refresh commands. the same rule applies to any access command after the auto refresh operation. all banks must be precharged prior to the auto refresh command. the refresh addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. the mobile-ram requires auto refresh cycles at an average periodic interval of 7.8 s (max.). partial array mode has no influence on auto refresh mode. figure 42 auto refresh = don't care cs cke (high) clk a0-a12 ba0,ba1 cas we ras ba a, row n = bank a, row n t rp t rc t rc = don't care dq high-z a10 (ap) row n pre all address ba a, row n command nop arf nop nop nop nop pre arf act clk
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description data sheet 38 v1.4, 2004-04-30 2.4.9.2 self refresh figure 43 self refresh entry command the self refresh command can be used to retain data in the mobile-ram , even if the rest of the system is powered down. when in the self refresh mode, the mobile-ram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is low. input signals except cke are ?don?t care? during self refresh. the procedure for exiting self refresh requires a stable clock prior to cke returning high. once cke is high, nop commands must be issued for t rc because time is required for a completion of any internal refresh in progress. the use of self refresh mode introduces the possibility that an internally timed event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh an extra auto refresh command is recommended. figure 44 self refresh entry and exit = don't care cs cke clk a0-a12 ba0,ba1 cas we ras table 13 timing parameters for auto refresh and self refresh parameter symbol - 7.5 units notes min. max. active to active command period t rc 67 ? ns 1) 1) these parameters account for the number of clock cycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period; round up to next integer. precharge command period t rp 19 ? ns 1) refresh period ( 8192 rows) t ref ?64ms 1) self refresh exit time t srex 1? t ck 1) t rp > t rc t rc t rc self refresh entry command self refresh exit command exit from self refresh any command (auto refresh recommended) = don't care t srex a10 (ap) pre all row n clk cke command nop arf nop nop nop pre arf act nop address ba a, row n dq high-z
data sheet 39 v1.4, 2004-04-30 hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description 2.4.10 power down figure 45 power down entry command power-down is entered when cke is registered low (no accesses can be in progress). if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding clk and cke. cke low must be maintained during power- down. power-down duration is limited by the refresh requirements of the device ( t ref ). the power-down state is synchronously exited when cke is registered high (along with a nop or deselect command). one clock delay is required for power down entry and exit. figure 46 power down entry and exit 2.4.10.1 deep power down the deep power down mode is an unique function on low power sdram devices with extremely low current consumption. deep power down mode is entered using the burst terminate command (cf. figure 35 ) except that cke is low. all internal voltage generators inside the device are stopped and all memory data is lost in this mode. to enter the deep power down mode all banks must be precharged. the deep power down mode is asynchronously exited by asserting cke high. after the exit, the same command sequence as for power-up initialization, including the 200s initial pause, has to be applied before any other command may be issued (cf. figure 3 and figure 4 ). = don't care cs cke clk ras a0-a12 ba0,ba1 we cas = don't care precharge power down mode shown: all banks are idle and trp met when power down entry command is issued any command power down entry t rp exit from power down high-z dq a10 (ap) valid pre all address valid command nop nop nop valid pre cke clk
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description data sheet 40 v1.4, 2004-04-30 2.5 function truth tables table 14 current state bank n - command to bank n current state cs ras cas we command / action notes any h x x x deselect (nop / continue previous operation) 1)2)3)4)5)6) 1) this table applies when cken-1 was high and cken is high and after t rc has been met (if the previous state was self refresh). 2) this table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3) current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4) the following states must not be interrupted by a command issued to the same bank. deselect or nop commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and according to table 15 . precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank is in the ?idle? state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank is in the ?row active? state. read with ap enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. write with ap enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. l h h h no operation (nop / continue previous operation) 1) to 6) idle l l h h active (select and activate row) 1) to 6) l l l h auto refresh 1) to 7) llllmode register set 1) to 7) llhlprecharge 1) to 6), 8) row active l h l h read (select column and start read burst) 1) to 6), 9) l h l l write (select column and start write burst) 1) to 6), 9) l l h l precharge (deactivate row in bank or banks) 1) to 6), 10) read (auto- precharge disabled) l h l h read (select column and start new read burst) 1) to 6), 9) l h l l write (select column and start new write burst) 1) to 6), 9) l l h l precharge (truncate read burst, start precharge) 1) to 6), 10) l h h l burst terminate 1) to 6), 11) write (auto- precharge disabled) l h l h read (select column and start read burst) 1) to 6), 9) l h l l write (select column and start write burst) 1) to 6), 9) l l h l precharge (truncate write burst, start precharge) 1) to 6), 10) l h h l burst terminate 1) to 6), 11)
data sheet 41 v1.4, 2004-04-30 hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description 5) the following states must not be interrupted by any exec utable command; deselect or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rc is met. once t rc is met, the sdram is in the ?all banks idle? state. accessing mode register: starts with registration of a mode register set command and ends when t mrd has been met. once t mrd is met, the sdram is in the ?all banks idle? state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks are in the idle state. 6) all states and sequences not shown are illegal or reserved. 7) not bank-specific; requires that all banks are idle and no bursts are in progress. 8) same as nop command in that state. 9) reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 10) may or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 11) not bank-specific; burst terminate affects the most recent read or write burst, regardless of bank. table 15 current state bank n - command to bank m (different bank) current state cs ras cas we command / action notes any h x x x deselect (nop / continue previous operation) 1)2)3)4)5)6) 1) this table applies when cken-1 was high and cken is high and after t rc has been met (if the previous state was self refresh). 2) this table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. l h h h no operation (nop / continue previous operation) 1) to 6) idle xxxxany command otherwise allowed to bank n 1) to 6) row activating, active, or precharging l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7) l h l l write (select column and start write burst) 1) to 7) l l h l precharge (deactivate row in bank or banks) 1) to 6) read (auto- precharge disabled) l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7) l h l l write (select column and start write burst) 1) to 8) l l h l precharge (deactivate row in bank or banks) 1) to 6) write (auto- precharge disabled) l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7) l h l l write (select column and start write burst) 1) to 7) l l h l precharge (deactivate row in bank or banks) 1) to 6) read (with auto- precharge) l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7), 9) l h l l write (select column and start write burst) 1) to 9) l l h l precharge (deactivate row in bank or banks) 1) to 6) write (with auto- precharge) l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7), 9) l h l l write (select column and start write burst) 1) to 7), 9) l l h l precharge (deactivate row in bank or banks) 1) to 6)
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram functional description data sheet 42 v1.4, 2004-04-30 3) current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read with ap enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. write with ap enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. 4) auto refresh, self refresh and mode register set commands may only be issued when all banks are idle. 5) a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6) all states and sequences not shown are illegal or reserved. 7) reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8) requires appropriate dqm masking. 9) concurrent auto precharge: bank n will start precharging when its burst has been interrupted by a read or write command to bank m. table 16 truth table - cke cken-1 cken current state command action notes l l power down x maintain power down 1)2)3)4) 1) cken is the logic state of cke at clock edge n; cken-1 was the state of cke at the previous clock edge. 2) current state is the state immediately prior to clock edge n. 3) command n is the command registered at clock edge n; action n is a result of command n. 4) all states and sequences not shown are illegal or reserved. self refresh x maintain self refresh 1) to 4) clock suspend x maintain clock suspend 1) to 4) deep power down x maintain deep power down 1) to 4) l h power down deselect or nop exit power down 1) to 4) self refresh deselect or nop exit self refresh 1) to 5) 5) deselect or nop commands should be issued on any clock edges occurring during t rc period. clock suspend x exit clock suspend 1) to 4) deep power down x exit deep power down 1) to 4), 6) 6) exit from deep power down requires the same command sequence as for power-up initialization. h l all banks idle deselect or nop enter precharge power down 1) to 4) bank(s) active deselect or nop enter active power down 1) to 4) all banks idle auto refresh enter self refresh 1) to 4) read / write burst (valid) enter clock suspend 1) to 4) h h see table 14 and table 15 1) to 4)
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram electrical characteristics data sheet 43 v1.4, 2004-04-30 3 electrical characteristics 3.1 operating conditions attention: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for ex tended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. table 17 absolute maximum ratings parameter symbol values unit min. max. power supply voltage v dd -0.3 2.7 v power supply voltage for output buffer v ddq -0.3 2.7 v input voltage v in -0.3 v ddq + 0.3 v output voltage v out -0.3 v ddq + 0.3 v operation case temperature commercial t c 0+70 c extended t c -25 +85 c storage temperature t stg -55 +150 c power dissipation p d ?0.7w short circuit output current i out ?50ma table 18 pin capacitances 1)2) 1) these values are not subject to production test but verified by device characterization. 2) input capacitance is measured according to jep147 with vdd, vddq applied and all other pins (except the pin under test) floating. dq?s should be in high impedance state. this may be achieved by pulling cke to low level. parameter symbol values unit min. max. input capacitance: clk c i1 1.5 3.0 pf input capacitance: all other input pins c i2 1.5 3.0 pf input/output capacitance: dq c io 3.0 5.0 pf
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram electrical characteristics data sheet 44 v1.4, 2004-04-30 table 19 electrical characteristics 1) 1) 0 c t c 70 c (comm.); -25 c t c 85 c (ext.); all voltages referenced to v ss . v ss and v ssq must be at same potential. parameter symbol values unit notes min. max. power supply voltage v dd 1.65 1.95 v ? power supply voltage for dq output buffer v ddq 1.65 1.95 v ? input high voltage v ih 0.8 v ddq v ddq + 0.3 v 2) 2) v ih may overshoot to v dd + 0.8 v for pulse width < 4 ns; v il may undershoot to -0.8 v for pulse width < 4 ns. pulse width measured at 50% with amplitude measured between peak voltage and dc reference level. input low voltage v il -0.3 0.3 v 2) output high voltage v oh v ddq - 0.2 ? v ? output low voltage v ol ?0.2v? input leakage current i il -1.0 1.0 a? output leakage current i ol -1.5 1.5 a?
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram electrical characteristics data sheet 45 v1.4, 2004-04-30 3.2 ac characteristics table 20 ac characteristics 1)2)3)4) 1) 0 c t c 70 c (comm.); -25 c t c 85 c (ext.); v dd = v ddq = 1.8 v 0.15 v; 2) all parameters assumes proper device initialization. 3) ac timing tests measured at 0.9 v. 4) the transition time t t is measured between v ih and v il ; all ac characteristics assume t t = 1 ns. parameter symbol - 7.5 unit notes min. max. clock cycle time cl = 3 t ck 7.5 ? ns ? cl = 2 9.5 ? ns clock frequency cl = 3 f ck ? 133 mhz ? cl = 2 ? 105 mhz access time from clk cl = 3 t ac ?5.4ns 5)6) 5) specified t ac and t oh parameters are measured with a 30 pf capacitive load only as shown below: 6) if t t (clk) > 1 ns, a value of ( t t /2 - 0.5) ns has to be added to this parameter. cl = 2 ? 6.0 ns clock high-level width t ch 2.5 ? ns ? clock low-level width t cl 2.5 ? ns ? address, data and command input setup time t is 1.5 ? ns 7) 7) if t t > 1 ns, a value of ( t t - 1) ns has to be added to this parameter. address, data and command input hold time t ih 0.8 ? ns 7) mode register set command period t mrd 2? t ck ? dq low-impedance time from clk t lz 1.0 ? ns ? dq high-impedance time from clk t hz 3.0 7.0 ns ? data out hold time t oh 2.5 ? ns 5)6) dqm to dq high-z delay (read commands) t dqz ?2 t ck ? dqm write mask latency t dqw 0? t ck ? active to active command period t rc 67 ? ns 8) 8) these parameter account for the number of clock cycles and depend on the operating frequency, as follows: no. of clock cycles = specified delay / clock period; round up to next integer. active to read or write delay t rcd 19 ? ns 8) active bank a to active bank b delay t rrd 15 ? ns 8) active to precharge command period t ras 45 100k ns 8) write recovery time t wr 14 ? ns 9) 9) the write recovery time of t wr = 14 ns allows the use of one clock cycle for the write recovery time when f ck 72 mhz. with f ck > 72 mhz two clock cycles for t wr are mandatory. infineon technologies recommends to use two clock cycles for the write recovery time in all applications. precharge command period t rp 19 ? ns 8) refresh period (8192 rows) t ref ?64ms? self refresh exit time t srex 1? t ck ? 30 pf i/o
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram electrical characteristics data sheet 46 v1.4, 2004-04-30 3.3 operating currents table 21 maximum operating currents 1) 1) 0 c t c 70 c (comm.); -25 c t c 85 c (ext.); v dd = v ddq = 1.8 v 0.15 v; recommended operating conditions unless otherwise noted parameter & test conditions symbol values unit notes - 7.5 operating current: one bank: active / read / precharge, bl = 1, t rc = t rcmin i dd1 60 ma 2)3) 2) these values are measured with t ck = 7.5 ns 3) all parameters are measured with no output loads. precharge power-down standby current: all banks idle, cs v ihmin , cke v ilmax , inputs changing once every two clock cycles i dd2p 0.5 ma 2) precharge power-down standby current with clock stop: all banks idle, cs v ihmin , cke v ilmax , all inputs stable i dd2ps 0.35 ma ? precharge non power-down standby current: all banks idle, cs v ihmin , cke v ihmin , inputs changing once every two clock cycles i dd2n 13 ma 2) precharge non power-down standby current with clock stop: all banks idle, cs v ihmin , cke v ihmin , all inputs stable i dd2ns 1.0 ma ? active power-down standby current: one bank active, cs v ihmin , cke v ilmax , inputs changing once every two clock cycles i dd3p 1.0 ma 2) active power-down standby current with clock stop: one bank active, cs v ihmin , cke v ilmax , all inputs stable i dd3ps 0.5 ma ? active non power-down standby current: one bank active, cs v ihmin , cke v ihmin , inputs changing once every two clock cycles i dd3n 15 ma 2) active non power-down standby current with clock stop: one bank active, cs v ihmin , cke v ihmin , all inputs stable i dd3ns 1.5 ma ? operating burst read current: all banks active; continuous burst read, inputs changing once every two clock cycles i dd4 45 ma 2)3) auto-refresh current: t rc = t rcmin , ?burst refresh?, inputs changing once every two clock cycles i dd5 90 ma 2) self refresh current: self refresh mode, cs v ihmin , cke v ilmax , all inputs stable i dd6 see table 22 ? deep power down current i dd7 20 a?
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram electrical characteristics data sheet 47 v1.4, 2004-04-30 3.4 pullup and pulldown characteristics the above characteristics are specified under nominal process variation / condition temperature ( t j ): nominal = 50 c, v ddq : nominal = 1.80 v table 22 self refresh currents 1)2) 1) 0 c t c 70 c (comm.); -25 c t c 85 c (ext.); v dd = v ddq = 1.8 v 0.15 v 2) the on-chip temperature sensor (octs) adjusts the refres h rate in self refresh mode to the component?s actual temperature with a much finer resolution than supported by the 4 distinct temperature levels as defined by jedec for tcsr. at production test the sensor is calibrated, and idd6 max. current is measured at 85c. typ. values are obtained from device characterization. parameter & test conditions max. temperature symbol values units notes typ. max. self refresh current: self refresh mode, full array activation (pasr = 000) 85 c i dd6 530 600 a? 70 c350? 45 c235? 25 c 215 ? self refresh current: self refresh mode, half array activation (pasr = 001) 85 c 365 415 70 c260? 45 c 185 ? 25 c165? self refresh current: self refresh mode, quarter array activation (pasr = 010) 85 c 285 325 70 c210? 45 c155? 25 c 140 ? table 23 half drive strength (default) and full drive strength voltage (v) half drive strength (default) full drive strength pull-down current (ma) pull-up current (ma) pull-down current (ma) pull-up current (ma) nominal low nominal high nominal low nominal high nominal low nominal high nominal low nominal high 0.00 0.0 0.0 -19.7 -33.4 0.0 0.0 -39.3 -66.7 0.40 15.1 20.5 -18.8 -32.0 30.2 41.0 -37.6 -63.9 0.65 20.3 28.5 -18.2 -31.0 40.5 57.0 -36.4 -61.9 0.85 22.0 32.0 -17.6 -29.9 43.9 64.0 -35.1 -59.8 1.00 22.6 33.5 -16.7 -28.7 45.2 67.0 -33.3 -57.3 1.40 23.5 35.0 -9.4 -20.4 46.9 70.0 -18.8 -40.7 1.50 23.6 35.3 -6.6 -17.1 47.2 70.5 -13.2 -34.1 1.65 23.8 35.5 -1.8 -11.4 47.5 71.0 -3.5 -22.7 1.80 23.9 35.7 3.8 -4.8 47.7 71.4 7.5 -9.6 1.95 24.0 35.9 9.8 2.5 48.0 71.8 19.6 5.0
hy[b/e]18l256160b[c/f]-7.5 256-mbit mobile-ram package outlines data sheet 48 v1.4, 2004-04-30 4 package outlines figure 47 p-vfbga-54-2 (plastic very thin fine ball grid array package) b 4) a 4) 8 x 0.8 = 6.4 0.8 +0.01 0.12 -0.04 20? 5? 2) 1) 3) d 5) 1.7 0.03 d 0.3 0.8 8 x 0.8 = 6.4 seating plane c c 0.1 c 0.1 -0.2 1.0 0.31 0.03 a 54x 0.41 0.03 ?0.07 ?0.12 c m m b 5) middle of ball matrix 4) middle of packages edges 2) die sort fiducial 3) bad unit marking (bum) 1) a1 marking ballside 1.5 12 4.25 2.24 8 2) 0.2 smd = surface mounted device you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . dimensions in mm
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